Latest Atrenta Press Releases

Atrenta Probes SpyGlass® Value at DAC

Wed, 30 May 2012 00:00:00 PST

SAN JOSE, Calif - May 30, 2012 - Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today the addition of an interview program at the 49th Design Automation Conference (DAC) to be held June 3-7, 2012 at San Francisco’s Moscone Center.� Customers, partners and investors will comment on how Atrenta’s SpyGlass® RTL analysis platform helps their business.

The interviews will be conducted at Atrenta’s booth (#2230) on the show floor of DAC between Monday, June 4 and Wednesday, June 6. The following individuals are currently scheduled to speak: Jack Browne (Sonics), Jim Hogan (private investor), Charlie Janac (Arteris), Dan Nenni (SemiWiki), Frederic Rivoallon (Xilinx) and Halim Theny (Vivante).� More speakers may be added, so check the latest schedule at the Atrenta booth during DAC.

Atrenta will also be unveiling a new brand identity for the company during the show. “Over the years, Atrenta has built a very strong franchise for RTL analysis with its SpyGlass product family,” said Mike Gianfagna, vice president of marketing at Atrenta. “That recognition and product loyalty simply cannot be bought, it must be earned. We are featuring the SpyGlass brand as part of Atrenta’s new identity.”

Response to Atrenta’s demo sessions has been very strong, with over 60 percent of all available demo slots pre-booked.� For more information on Atrenta’s DAC activities or to book a demo session, visit
http://www.atrenta.com/DAC2012/.

About Atrenta

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

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For more information, contact:

Atrenta:
Charu Puri
Tel: +1-408-453-3333
Email: cpuri@atrenta.com

PR Agency:
Lee PR
Liz Massingill
Tel: +1-650-363-0142
Email: liz@leepr.com

Atrenta Ships 4.7 Release of SpyGlass® Platform

Tue, 01 May 2012 08:00:00 PST

SAN JOSE, Calif - May 1, 2012 - Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today the availability of release 4.7 of its SpyGlass® RTL analysis and optimization platform.

This latest release of SpyGlass delivers automated RTL power reduction that is, on average, 2X more effective across a broad range of designs when compared to previous releases. Run-time and memory usage have also been enhanced in 4.7 – customers have reported running 280 million gate designs flat through SpyGlass in four hours.

Many of the analysis features of SpyGlass have also been improved. UPF 2.0 support has been extended in SpyGlass Power Verify. A unique power intent-aware CDC analysis has been introduced that enables early verification of CDC issues around isolation logic at RTL. Glitch detection reporting has been enhanced and SpyGlass DFT DSM now provides at-speed testability analysis that is more comprehensive. SpyGlass Constraints analysis now enables designers to consolidate SDCs associated with different modes into a single SDC through an SDC mode merge capability.

New features in SpyGlass 4.7 include an improved user interface for SpyGlass Physical that provides designers the capability to quickly analyze and pinpoint logical congestion issues within their RTL. Also included in this release is a unique design complexity analysis addition to SpyGlass Advanced Lint based on cyclomatic metrics. The Atrenta Console graphical user interface also provides several usability enhancements for netlist and schematic viewing.

"The SpyGlass platform is helping our customers produce higher quality RTL, resulting in faster time to market and improved IP reuse," said Mike Gianfagna, vice president of marketing at Atrenta. "The 4.7 release of the platform contains many enhancements and several new features that respond directly to our customer's requests. I am confident the new version will see wide deployment."

About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With nearly 200 customers, including 19 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements

For more information, contact:

Atrenta:
Charu Puri
Tel: +1-408-453-3333
Email: cpuri@atrenta.com

PR Agency:
Lee PR
Liz Massingill
Tel: +1-650-363-0142
Email: liz@leepr.com

Atrenta Expands Technical Advisory Board in Europe

Tue, 24 Apr 2012 00:00:00 PST

GRENOBLE, France - April 24, 2012 - Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today the creation of a European technical advisory board (TAB). This group expands the existing Atrenta TAB , which is composed of high-profile researchers and professors in the US and Asia. The expansion of its TAB into Europe supports Atrenta’s growing R&D center there, co-located at the MINATEC innovation campus in Grenoble.

The new Atrenta European TAB is composed of distinguished and highly accomplished experts who will provide strategic guidance to Atrenta on issues related to advanced power reduction, physical design (including 3D), formal verification, technology trends and the latest research in SoC design and manufacturing.
"I am delighted to have such a talented and diverse group of researchers working with us," said Mo Movahed, vice president of engineering at Atrenta. "I am confident that this group will make substantial contributions to Atrenta’s product development strategy. We are looking forward to collaborating on advanced research as well."

Atrenta's new European TAB members include: Professor Lorena Anghel (TIMA Laboratory), Professor Rolf Drechsler (Group of Computer Architecture of Universität Bremen), Professor Wolfgang Kunz (University of Kaiserslautern) and Dr. Oded Maler (VERIMAG). Please see Atrenta’s TAB page for more details on other TAB members and their biographies.

About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With nearly 200 customers, including 19 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com.

© 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass and GenSys are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

Atrenta:
Charu Puri
Tel: +1-408-453-3333
Email: cpuri@atrenta.com

PR Agency:
Lee PR
Liz Massingill
Tel: +1-650-363-0142
Email: liz@leepr.com

Atrenta Offers IP Kit Spring Cleaning Promotion

Mon, 16 Apr 2012 00:00:00 PST

SAN JOSE, Calif. - April 16, 2012 - Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, is offering semiconductor design groups access to the Atrenta IP Kit through a free 2-week trial promotion.

From April 16, 2012 to May 31, 2012, qualified design groups in the US will be able to use Atrenta's IP Kit to perform "spring cleaning" on their third-party or internally developed IP blocks for two consecutive weeks at no cost. Atrenta's IP Kit is also used by TSMC to quality soft IP for inclusion in the TSMC 9000 IP library. (See the March 2011 press announcement for more details and a list of the IP providers participating in the program.)

"By enabling design groups to develop 'SpyGlass® Clean' IP blocks, they can realize more predictable design cycles and faster time to market," said Mike Gianfagna, vice president of marketing at Atrenta. "I am confident that many people will discover substantial opportunities to improve the quality of their IP libraries as a result of the program."

Atrenta's IP Kit helps SoC designers to confront IP re-use challenges, such as design completeness, power consumption, testability, subtle integration risks, managing updates/bug fixes and even finding the right IP. The Atrenta IP Kit offers the following user benefits:

IP quality metrics – easy to read HTML-based DashBoard and DataSheet reports
Automated SpyGlass setup – easy to use & run
Comprehensive handoff checks - simulation-synthesis mismatch, electrical, clock domain crossing verification, testability analysis (stuck-at & at-speed), power estimation and verification of timing constraints
IP packaging support
Ease of integration into existing design flows

For more details on the IP Kit Spring Cleaning promotion, please visit: http://www.atrenta.com/springclean/.

© 2012 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, and SpyGlass are registered trademarks of Atrenta Inc. GenSys is a trademark of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

For more information, contact:

Atrenta:
Charu Puri
Tel: +1-408-453-3333
Email: cpuri@atrenta.com

PR Agency:
Lee PR
Liz Massingill
Tel: +1-650-363-0142
Email: liz@leepr.com

Atrenta Will Discuss IP Quality at DATE Panel Session

Tue, 13 Mar 2012 00:30:00 PST

DRESDEN, Germany

What:
Dr. Fahim Rahim, Director of Engineering at Atrenta will participate in the upcoming panel session - "Not Me! Who Really Owns the IP Quality Issue?" - at DATE 2012.

IP quality is described as crucial to SoC design. But what is "quality" in IP? How do you measure it?

This panel will attempt to define IP quality and the metrics of an IP quality measurement process. By doing so, the panel will strive to reduce the finger pointing...but it may, in fact, instigate a new round, as the participants debate where the buck stops when it comes to using and re-using IP in an efficient, predictable and scalable manner.

Dr. Rahim will discuss the increasingly complex use of IP and what is needed to measure the quality - and improve the use - of IP in the design environment. Other panelists include:

• Simon Butler, CEO, Methodics Inc.
• Gabriele Saucier, President, Design and Reuse
• Andreas Bruning, Director, Technology Office, ZDMI
• Gerd Teepe, Director Design Enablement, GLOBALFOUNDRIES

Gary Smith, a well-known industry analyst and founder of Gary Smith EDA, will moderate the panel.

When:
1:15 pm - 2:15 pm CET, Wednesday, March 14 at DATE 2012

Where:
Exhibition Theatre
DATE
Maritim Hotel & Internationales Congress Center Dresden
Ostra-Ufer 2
01067 Dresden, Germany

Why:
After attending the panel, the audience should have a more comprehensive, working knowledge of the meaning and measurement of IP quality, and how to use reuse IP in a more efficient, predictable and scalable manner.

For more information, contact:

Atrenta
Tiffany Sparks
Tel: +1-408-467-4280
Email: tiffany@atrenta.com

PR Agency:
Lee PR
Liz Massingill (liz@leepr.com)
Tel: +1-650-363-0142

This press advisory contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press advisory.

Atrenta and TSMC IP Quality Initiative Gains Broad Industry Acceptance

Mon, 05 Mar 2012 06:00:00 PST

SAN JOSE, Calif. - March 5, 2012 - Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that 10 intellectual property (IP) providers have qualified their soft IP for inclusion in the TSMC 9000 IP library using the Atrenta IP Handoff Kit.

Those companies, part of TSMC's Soft-IP Alliance Program, include Arteris, Inc.; CEVA; Chips&Media, Inc.; Digital Media Professionals Inc. (DMP); Imagination Technologies; Intrinsic-ID; MIPS Technologies, Inc.; Sonics, Inc.; Tensilica, Inc.; and Vivante Corporation. The participating companies are able to provide quantitative information to TSMC's customers regarding the robustness and completeness of their soft or synthesizable semiconductor IP that is part of the TSMC 9000 IP library.

In May 2011, TSMC and Atrenta announced the Soft-IP Alliance Program, which uses Atrenta's SpyGlass® platform and a targeted subset of its GuideWare reference methodology to implement TSMC's IP quality assessment program. TSMC requires all soft IP providers to reach a minimum level of completeness, as documented by Atrenta DashBoard and DataSheet reports, before their IP is listed on TSMC online.

Atrenta integrated all the software and methodologies needed to implement TSMC's IP qualification requirements to form the IP Handoff Kit, which uses the SpyGlass register transfer level (RTL) analysis and optimization product suite. To qualify for inclusion in TSMC Online, soft IP must be verified for language syntax and semantic correctness, simulation-synthesis mismatches, electrical and connectivity rules, power consumption, synchronization of clock domain crossing paths, stuck-at and at-speed test coverage and timing constraints. All results are summarized in Atrenta DashBoard and DataSheet reports that capture the results of these SpyGlass tests in an easy-to-read and track HTML format.

"Given the complexity inherent in today's system on chip (SoC) designs, TSMC is proactively helping our customers mitigate risk and meet their time-to-market goals," said Suk Lee, director, Design Infrastructure Marketing Division, TSMC. "The IP qualification flow with Atrenta addresses many of the quality challenges inherent in re-using third-party IP. We are pleased with the number of IP providers that are participating in this program and the measurable improvement in delivered IP quality available for TSMC's end customers."

"As designers face the challenge of finding quality third-party IP, this program – a collaboration between TSMC, Atrenta and IP providers – is a powerful example of what teamwork in the supply chain can accomplish," said Mike Gianfagna, vice president of marketing at Atrenta. "TSMC customers can now make more informed decisions that improve the handoff of IP between members of the semiconductor supply chain. This is one way to drive more effective SoC Realization."

About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys™ products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With nearly 200 customers, including 19 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com.

Atrenta and TSMC IP Quality Initiative Gains Broad Industry Acceptance

Partner Quotes

Arteris
"Based on our long-standing relationship with TSMC, Arteris is pleased to participate in TSMC's Soft-IP Alliance Program and TSMC Reference Flows 11 and 12. By validating Arteris' configurable NoC interconnect IP with the SpyGlass platform, customers can choose our IP and handoff their design to TSMC with even greater confidence."

K. Charles Janac
President and CEO
Arteris

CEVA
"CEVA is committed to streamlining the SoC design process and supply chain through a robust ecosystem that improves the efficiency of how customers use our DSP-based solutions. The link to the manufacturing process is critical as we move into the realm of 28 nanometer and beyond. We are pleased to be able to work with Atrenta and TSMC to certify our IP using TSMC's soft IP validation kit. This will result in faster and more reliable manufacturability for our customers."

Moshe Sheier
Director of Product Marketing
CEVA, Inc.

Chips & Media
"As consumers demand a better experience from their multimedia devices, SoC designs are becoming more complex. By working closely with TSMC and Atrenta, Chips&Media is capable of delivering its leading-edge video processing technologies to customers more efficiently and effectively."

Steve Kim
CEO
Chips&Media,Inc.

Digital Media Professionals
"In support of our advanced graphics IP technology based on industry-standard OpenGL ES and DMP's proprietary Maestro extension, we are able to leverage excellent semiconductor process technology from TSMC and comprehensive assessment metrics from Atrenta. With a wide-range of leading-edge technologies and eco-system support, DMP will provide highly optimized and validated graphics IPs for embedded markets."

Tatsuo Yamamoto
President & CEO
Digital Media Professionals Inc.

Intrinsic-ID
"As SoC devices become more prevalent and customer needs become increasingly more complex, Intrinsic-ID offers a wide-ranging portfolio of IP available in the TSMC 9000 IP library. Working with TSMC and Atrenta, the quality of our IP is demonstrated and customers will be more informed when using it in their designs, reducing the risk in the handoff to other members of the supply chain."

Pim Tuyls
CEO
Intrinsic-ID

MIPS
"The Atrenta IP Handoff Kit can help assure customers of quality and consistency across the variety of IP available for use at TSMC. As a member of the TSMC Soft IP Alliance Program, MIPS Technologies is committed to working closely with TSMC to speed our customers' time-to-market. Starting with our superscalar multicore MIPS32® 1074K™ coherent processing system, MIPS is leveraging the IP Handoff Kit to validate that our IP meets and surpasses TSMC's expectations of quality for soft IP."

Gideon Intrater
Vice President of Marketing
MIPS Technologies, Inc.

Sonics
"As the number of unique IP cores increase with each process node, the need for a reliable, high-performance on-chip network is critical for successful SoC execution. As a partner in the Atrenta and TSMC IP Quality Initiative, and a TSMC Soft IP Alliance member, Sonics gives customers complete assurance and support from the initial design to TSMC hand-off. Our partnership with Atrenta continues to help semiconductor leaders realize their broad range of SoC designs, and the SpyGlass product suite will continue to play an integral part of Sonics' RTL flow."

Frank Ferro
Director of Marketing
Sonics

Tensilica
"Tensilica is pleased to participate in TSMC's Soft-IP Alliance Program after many years of producing successful tapeouts for mutual customers. By validating our IP against quality metrics established by TSMC and measured using the SpyGlass platform, our customers can choose Xtensa processors and deliver their designs to TSMC with even greater confidence."

Chris Jones
Director, Product Marketing
Tensilica, Inc.

Vivante
"Vivante is pleased to be part of TSMC's Soft-IP Alliance Program, offering customers our full line of high performance, power efficient GPU/GPGPU cores. By going through extensive validation of our IP on the SpyGlass platform to ensure reliability and quality, customers can be confident that selecting Vivante products will reduce their risk and expedite time to market of their designs."

Wei-Jin Dai
President and CEO
Vivante Corporation

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

For more information, contact:
Atrenta:
Tiffany Sparks
Tel: +1-408-467-4280
Email: tiffany@atrenta.com

PR Agency:
Lee PR
Liz Massingill
Tel: +1-650-363-0142
Email: liz@leepr.com

Atrenta CFO Bert Clement to Present at 14th Annual Needham Growth Stock Conference

Mon, 09 Jan 2012 06:00:00 PST

NEW YORK -- January 9, 2012

Who:
Bert Clement, Chief Financial Officer of Atrenta, a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries

What:
To Present at the 14 th Annual Needham Growth Stock Conference

When:
Tuesday, January 10, 2012 at 11 am EST

Where:
New York Palace Hotel, New York, in the Campbell Room

Note:
Mr. Clement will be available to meet with investors as well

About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys™ products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With nearly 200 customers, including 19 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com.

For more information, contact:

Atrenta:
Tiffany Sparks
Tel: +1-408-858-1892
Email: tiffany@atrenta.com

PR Agency:
Lee PR
Liz Massingill (liz@leepr.com)
Tel: +1-650-363-0142

Atrenta, SpyGlass and the Atrenta logo are registered trademarks, and GenSys is a trademark of Atrenta Inc. All others are the property of their respective holders.
This press advisory contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press advisory.

Atrenta Will Discuss SoC Realization at VLSI India Conference 2012

Tue, 03 Jan 2012 09:00:00 PST

New Delhi, India

What:

Mr. Sathyam Pattanam, Senior Director Engineering for GenSys™ and SpyGlass® Low Power Verification Products at Atrenta, will participate in a panel entitled "SoC Realization � A Bridge to New Horizons or a Bridge to Nowhere?" at the VLSI Design Conference 2012.

System on Chip (SoC) Realization is the emerging market that bridges the gap between an electronic system concept and its implementation in silicon.

In the panel, Mr. Pattanam will discuss the merits of early analysis methodologies and solutions, together with panelists from other semiconductor and EDA companies including:

Broadcom - Subhash Chintamaneni, Senior Manager, DTV Division
Cadence � Raju Pudota, Group Director, Flash IP Engineering
Freescale � Ganesh Guruswamy, Vice President and Country Manager
InfoTech Enterprises � Ram Gollapudi, General Manager, Hi-tech Business Unit
Seer Akademi � Srikanth Jadcherla, Chairman and CEO, Electronics Education Company
ST � Rajamohan Varambally, Director Technology R&D
Synopsys � Vikas Gautam, Director, Verification and IP products
TI �Mahesh Mehendale, TI Fellow and Director, Center of Excellence for VLSI Architectures

Professor P.P. Chakrabarti, IIT Kharagpur, will moderate the panel to explore and discuss the meaning of SoC Realization and its impact on the cost and schedule for advanced SoC designs.

When:
January 9, 2012 from 5:25pm to 6:40pm IST

Where:
VLSID 2012, HICC, Hyderabad, India

Why:
SoC design promises to revolutionize a vast array of products and markets, but the cost of design for SoC devices is growing at a rapid pace. Shrinking market windows necessitate reuse of semiconductor IP, either from third-party sources or prior internal designs. But the quality and completeness of this IP is often not completely known. Structured design methodologies that focus on early identification and correction of design issues, rigorous methods to qualify semiconductor IP and automated approaches to assembling the components of an SoC promise to address many of the cost and schedule challenges.

Notes:

For information about the VLSID Conference, visit: http://vlsiconference.com/vlsi2012/ .

For more information, contact:

Atrenta
Charu Puri
Tel: +91-9810313320
Email: cpuri@atrenta.com

PR Agency
Lee PR
Liz Massingill (liz@leepr.com)
Tel: +1-650-363-0142

Atrenta, the Atrenta logo and SpyGlass are registered trademarks, and GenSys is a trademark of Atrenta Inc. All others are the property of their respective holders.
This press advisory contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press advisory.

Atrenta Introduces Early PPA Analysis at ARM TechCon 2011

Mon, 24 Oct 2011 09:00:00 PST

What:
Using ARM's AMBA® Designer and its SpyGlass® and GenSys® product families, Atrenta will demonstrate how to perform Early PPA analysis on AMBA-based designs.

When:
Tuesday, October 25, 2011

Where:
ARM TechCon 2011
Santa Clara Convention Center
Santa Clara, CA.
Table #19

Why:

Defining the correct interconnect architecture for complex system on chip (SoC) designs can be challenging, requiring multiple back-end iterations. Early PPA analysis can reduce these iterations by helping to answer questions about the design up-front, such as:

1. What is the performance, power and area of the SoC being planned (PPA)?
2. Can �what-if� analysis be quickly performed to zoom-in on a high-confidence architecture?
3. Can I capture architectural intent, validate it and provide forward guidance for implementation?

Notes:
• For information about the ARM TechCon 2011, visit: http://events.ubm.com/event/1153/the-arm-technology-conference

For more information, contact:
Corporate:
Tiffany Sparks
Tel: +1-408- 467-4280
Email: tiffany@atrenta.com

PR Agency:
Lee PR
Tel: +1-650-363-0142
Email: liz@leepr.com

****************
Atrenta, SpyGlass, GenSys and the Atrenta logo are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press advisory contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press advisory.

Atrenta Joins Cadence System Realization Alliance

Mon, 24 Oct 2011 09:00:00 PST

San Jose, Calif. � Oct. 24, 2011 � Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that it has joined the Cadence System Realization Alliance. The initial focus for the alliance will be to verify that output of the Cadence® C-to-Silicon Compiler passes a set of high-level synthesis SpyGlass® rules that will be jointly developed by Cadence and Atrenta.

The Cadence C-to-Silicon Compiler automatically generates synthesizable register transfer level (RTL) output starting from untimed C/C++/SystemC® . Atrenta's SpyGlass is the widely used platform for validation and optimization of RTL descriptions prior to handoff to physical design tools. Through this collaboration, Cadence and Atrenta will define a set of SpyGlass rules that verify C-to-Silicon output for parameters such as syntactic correctness, power, testability and clock synchronization. It is anticipated that the resultant rules will become part of C-to-Silicon internal testing, and a subset of these rules will also be available to end users.

�High-level synthesis is moving into mainstream design practice, and the technology will be a key ingredient for ensuring our customers' success,� said Ramesh Dewangan, senior director, product marketing for the SpyGlass platform at Atrenta. �We are delighted to be part of the Cadence System Realization Alliance. Together, Atrenta and Cadence can enable Cadence customers to reap the benefits of faster time to market provided by high-level synthesis solutions.�

�Cadence is committed to providing our C-to-Silicon customers with industry-leading quality of results and a superior user experience,� said Michal Siwinski, group director of product marketing, System & Software Realization Group, Cadence . �Our alliance with key companies like Atrenta ensures we can continue to deliver the C-to-Silicon solutions required to reduce time-to-market and design complexity.�

About Atrenta

Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 19 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com.
*******************************************************
© 2011 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass and GenSys are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

Atrenta CEO Presents Keynote at Si2 Conference

Tue, 18 Oct 2011 00:00:00 PST

What:
Dr. Ajoy Bose, Chairman, President and CEO of Atrenta, will deliver the keynote at the 16 th Si2 Conference.

In his keynote address entitled "SoC Realization � Building a Bridge to New Markets and Renewed Growth," Dr. Bose will discuss how "getting it right" during the SoC Realization phase of the design process could lead to the creation of new markets and renewed growth for the industry.

When:
Thursday, October 20, 2011
9:45 AM - 10:30 AM, Pacific Time

Where:
16 th Si2 Conference
Network Meeting Center at Techmart
5201 Great America Parkway, Santa Clara, CA 95054

Why:
SoC Realization is where high-level concepts are refined to implementation readiness. Legacy and third - party IP blocks are chosen and integrated and the overall chip is prepared for back-end implementation . Getting it right at this stage will dramatically reduce implementation challenges and iteration times, but first, completing the flow and implementing the vision will require the collaboration of many.

Notes:

• For information about the Si2 Conference, visit: http://www.si2.org.

For more information, contact:
Corporate:
Tiffany Sparks
Tel: +1-408- 467-4280
Email: tiffany@atrenta.com

PR Agency:
Lee PR
Liz Massingill (liz@leepr.com)
Tel: +1-650-363-0142

********************************************
Atrenta, SpyGlass and the Atrenta logo are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This press advisory contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press advisory.

Atrenta to Present Soft IP Qualification Flow at TSMC Event

Thu, 13 Oct 2011 00:00:00 PST

This paper will give an overview and details regarding what aspects of the IP are checked and how the information is used to assess IP completeness, readiness and integration risks. This paper will also review the process needed to install, setup and run the software and share some results of its application on production-level soft IP blocks.

Who:
Anuj Kumar, Sr. Manager of the Customer Consulting Group at Atrenta

When:
Tuesday, October 18, 2011; 1:00 PM - 1:30 PM, Pacific Time

Where:
TSMC Open Innovation Platform Ecosystem Forum, San Jose Convention Center, San Jose, Calif., USA.

Why:
As much as 80% of an SoC (system on chip) may be comprised of soft IP blocks. It's crucial for SoC designers to know the quality, completeness and integration risks associated with the soft, or synthesizable semiconductor IP they use. This knowledge is critical to meeting power, performance, area and schedule targets for complex SoC designs.

Atrenta has collaborated with TSMC to create a comprehensive system to automate the process of soft IP qualification. Based on the Atrenta SpyGlass® platform, the system programmatically analyzes soft IP using an IP handoff methodology consisting of TSMC's Golden Rule Set covering various design parameters (e.g., risk analysis, integration readiness, implementation readiness, reusability) for a soft IP block.

Notes:
• Atrenta is exhibiting at booth #213
• For information about the TSMC OIP Ecosystem forum, please visit:
https://www.lookingcube.com/tsmc/OIPEcosystemforum/information.asp

For more information, contact:
Corporate:
Tiffany Sparks
Tel: +1-408- 467-4280
Email: tiffany@atrenta.com

PR Agency:
Lee PR
Liz Massingill (liz@leepr.com)
Tel: +1-650-363-0142

*********************

Atrenta, SpyGlass and the Atrenta logo are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This press advisory contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press advisory.

Atrenta Focuses on IP Quality, Chip Assembly and RTL Hand-off in Upcoming Seminar Series

Thu, 18 Aug 2011 09:00:00 PST

SAN JOSE, Calif. - August 18, 2011 - Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced plans for a seminar series that presents new solutions and methodologies to accelerate quality IP selection, IP integration and SoC assembly, and successful RTL hand-off.

The series, "Fast Track Your SoC Design," is currently scheduled in four locations worldwide:

Ottawa, Canada - Tuesday, September 13, 2011

Austin, Texas - Tuesday, September 20, 2011

Santa Clara, Calif. - Tuesday, September 27, 2011

Bangalore, India - Thursday, October 13, 2011

Additional locations will be scheduled at a later date.

The events will feature presentations from Atrenta design and product experts, as well as Atrenta customers, examining the challenges designers encounter as they look for IP, qualify it, pick the right architecture, assemble the SoC, and get it ready for RTL handoff � all while being pressured by shrinking time-to-market windows and cost constraints.

"As any missteps in the design process today may lead to lengthy delays and additional costs, designers can quickly find themselves in design gridlock," said Mike Gianfagna, vice president of marketing at Atrenta. "In this seminar series, we will explain how Atrenta's advanced methodologies and solutions for SoC analysis and assembly can help you fast track your SoC design with greater confidence, bypassing design gridlock and successfully handing off at RTL."

To register or for more information on the seminar series, please visit http://www.atrenta.com/fastracksoc

About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com.

*******************************************************

© 2011 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass and GenSys are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

For more information, contact:

Corporate:
Tiffany Sparks
Tel: +1-408- 467-4280
Email: tiffany@atrenta.com

PR Agency:
Lee PR
Ed Lee (ed@leepr.com)
Liz Massingill (liz@leepr.com)
Tel: +1-650-363-0142

Fujitsu Kyushu Network Technologies Limited Adopts Atrenta's SpyGlass® AutoVerify for RTL Functional Checks

Mon, 06 Jun 2011 09:00:00 PST

San Diego, Calif. - June 6, 2011 - Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced at the Design Automation Conference here that Fujitsu Kyushu Network Technologies Limited has adopted its SpyGlass® AutoVerify for Advanced Lint analysis to achieve design quality of results (QoR) and design productivity improvements in their ASIC/FPGA flows.

Atrenta has recently extended its SpyGlass family by adding an Advanced Lint feature, which uses formal verification techniques to detect hard-to-find design problems early - and fix them even before functional verification begins. Advanced Lint capabilities include extensive finite state machine (FSM) checks and audit capabilities, dead code checks, parallel and full-case pragma verification, bus contention and floating bus detection. As part of the SpyGlass platform, the solution provides extensive support for VHDL and Verilog as well as System Verilog.

Fujitsu Kyushu Network Technologies Limited performed rigorous evaluation of the Advanced Lint capability and identified several critical problems in RTL through its use.

"With verification taking as much as 70% of total design cycle time, we believe that verification at the early stages of design can provide significant improvement in productivity," said Yuji Yoshitani, Senior Engineer, Development Dept.II, System logic Development Center at Fujitsu Kyushu Network Technologies Limited . "With SpyGlass AuoVerify , we were able to identify deeper RTL issues using formal technologies which are hard-to-find using basic linting or a simulation based methodology. SpyGlass AutoVerify enables us to check "RTL activation status", such as checking dead code, FSM deadlocks, unreachable states, static registers and initialized values of registers."

"Atrenta's SpyGlass is already a de-facto industry standard in linting solutions, and the only platform to perform RTL analysis for linting, power, DFT, clock domain crossing, timing constraints and routing congestion," said Ramesh Dewangan, senior director, product marketing for the SpyGlass platform at Atrenta. "Fujitsu Kyushu Network Technologies Limited's adoption of our SpyGlass Advanced Lint solution further validates the enhanced value of our SpyGlass platform."

About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com.

*******************************************************

© 2011 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass and GenSys are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

For more information, contact:
Corporate:
Charu Puri, Corporate Marketing
Tel: +1-408- 467-4254
Email: cpuri@atrenta.com

PR Agency:
Lee PR
Ed Lee (ed@leepr.com)
Liz Massingill (liz@leepr.com)
Tel: +1-650-363-0142

Atrenta CEO Dr. Ajoy Bose to Speak on "Hogan's Heroes" Panel at Design Automation Conference

Wed, 01 Jun 2011 09:00:00 PST

Who: Dr. Ajoy K. Bose, Chairman, president & CEO, Atrenta Inc.

What: Panel: "Hogan's Heroes: The Reaggregation of Ecosystem Value"

Abstract:
The semiconductor ecosystem shifts its value aggregation on somewhat predictable cycles. These are followed by longer periods of stability during which new companies are created. The latest cycle is being driven by system houses. What impact will these new trends in system design have on EDA and IP business models and enterprise value?

When: Tuesday, June 7, 2011; 11:00 AM - 12:00 PM

Where: Booth #3421 at Design Automation Conference (DAC) 2011

Moderator: Jim Hogan / Tela Innovation, Inc., Campbell, CA

Atrenta and the Atrenta logo are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press advisory contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press advisory.

For more information, contact:
Corporate:
Charu Puri, Corporate Marketing
Tel: +1-408-493-3514
Email: cpuri@atrenta.com

PR Agency:
Lee PR
Ed Lee (ed@leepr.com)
Liz Massingill (liz@leepr.com)
Tel: +1-650-363-0142

Atrenta Announces a New Text Book on RTL Design

Tue, 31 May 2011 09:00:00 PST

San Jose, Calif. - May 31, 2011 - Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced the availability of a comprehensive text book on RTL design. The text book "Principles of VLSI RTL Design, A Practical Guide", authored by Sanjay Churiwala and Sapan Garg is being published by Springer Science+Business Media. The book is based on the author's experiences while working at Atrenta's Noida, India R&D center.

"Through our years of work at Atrenta, we had seen a lot of designs and design methodologies. We developed a good understanding of what best practices looked like," said Sanjay Churiwala. "It was gratifying to be able to put all those ideas down on paper so others can benefit from our experiences."

The book targets RTL designers and provides rich information on design practices and how they affect downstream implementation tasks. Topics discussed in the text include: reliable RTL construction, clock domain crossings and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling and routing congestion.

"The decisions made by RTL designers can have a profound impact on the schedule and ultimate quality of the chip," said Sapan Garg. "Through the use of many examples, we highlight how the RTL designer can heavily influence the outcome of any design project."

The book is available now through Springer ( www.springer.com ) or at Amazon.com.

About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com.

*******************************************************

© 2011 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass and GenSys are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

Atrenta Announces SpyGlass Tool Used in TSMC Soft IP Qualification Flow

Thu, 26 May 2011 09:00:00 PST

San Jose, Calif. and HSINCHU, Taiwan, R.O.C. - May 26, 2011 - Atrenta Inc. today announced the deployment of a comprehensive soft IP qualification program using Atrenta's SpyGlass® platform and a targeted subset of its GuideWare reference methodology in TSMC's IP quality assessment program. The goal of the program is to provide quantitative information to TSMC's customers regarding the robustness and completeness of synthesizable semiconductor IP that is part of the TSMC 9000 IP library. All the software and methodologies needed to implement TSMC's IP qualification requirements have been integrated by Atrenta to form the IP Handoff Package.

TSMC is using the SpyGlass register transfer level (RTL) analysis and optimization product suite for soft, or synthesizable IP handoff. To qualify for handoff, the IP must be verified for language syntax and semantic correctness, simulation-synthesis mismatches, electrical and connectivity rules, power consumption, synchronization of clock domain crossing paths, stuck-at and at-speed test coverage and timing constraints. Also required for the IP handoff are automatically generated Atrenta DashBoard and DataSheet reports that capture the results of these SpyGlass tests in easy to read and track HTML format. Atrenta has worked with TSMC over the past nine months to refine the specific tests to be performed and optimize the format of the DashBoard and DataSheet reports.

TSMC will require all soft IP providers to reach a minimum level of completeness, as documented by the DashBoard and DataSheet reports, before their IP is listed on TSMC online. "TSMC places high importance on the quality of deliverables from our IP ecosystem," said Suk Lee, director, Design Infrastructure Marketing Division, TSMC . "We have worked closely with Atrenta to refine the process of validating the delivered quality of soft IP from our ecosystem partners. The capability we are now putting into production is expected to provide valuable information regarding soft IP quality for our end customers."

Starting with the Atrenta GuideWare reference methodology, TSMC and Atrenta have defined a subset of the methodology which is targeted at verifying the quality and completeness of soft IP design blocks. This methodology has been packaged along with training materials, a test IP design and the scripts necessary to analyze the IP and generate the DashBoard and DataSheet reports. The companies have tested this package with multiple TSMC IP ecosystem partners.

"Starting with known good IP is a critical requirement for effective SoC Realization," said Dr. Ajoy Bose, chairman, president and CEO of Atrenta. "We are confident in the ability of our SpyGlass product to improve the handoff of IP between members of the semiconductor supply chain. I am delighted that TSMC has chosen Atrenta to help implement its forward-looking soft IP qualification program."

About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com
*******************************************************

Atrenta, the Atrenta logo, SpyGlass and GenSys are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

Imec and Atrenta Develop Exploration Flows for 3D ICs

Tue, 24 May 2011 21:00:00 PST

Leuven, Belgium and San Jose, Calif., - May 24, 2011 - Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, in collaboration with imec's 3D integration IIAP (industrial affiliation program), have jointly developed an advanced planning and partitioning design flow for heterogeneous 3D stacked ICs. Imec and Atrenta will be demonstrating this flow at the Design Automation Conference (DAC) in San Diego, CA from June 6 - 8, 2011.

A flow allowing robust, accurate partitioning and prototyping early in the design process is critical to make cost-effective 3D systems and to get them to market fast. The flow under development allows minimizing the number of design iterations, facilitating a cost- and time-effective search of the solution space. Imec and Atrenta demonstrated their first EDA tool flow dedicated to 3D design exploration at last year's DAC.

3D stacked ICs are a promising technology for many designers. The main advantages are a reduced footprint with shorter and faster interconnects, increased system integration at a lower cost, and higher modularity and reuse. Examples of target applications include: products for mobile and high-performance applications, imagers, stacked DRAM, and solid-state drives.

To design innovative applications with 3D stacked dies, the ability to do early planning and partitioning is critical. The number of potential solutions for any given system design problem (e.g., front to front, front to back, silicon interposer, technology choice for slices, via configurations, partitioning, etc.) is very large. Exploring this solution space through multiple full designs is simply too expensive and time-consuming. This makes it critically important to perform robust, accurate partitioning and prototyping early in the design process, well before detailed implementation begins.

There are other significant challenges for 3D design, such as the thermal profiles (heat dissipation) and the mechanical stress caused by assembly configurations. Imec has developed compact thermal and mechanical models for rapid generation of heat dissipation and mechanical stress maps and has validated them using real 3D DRAM-on-logic packaged devices. When combining the design floor plans produced by Atrenta's SpyGlass® Physical 3D prototyping tool with the stress models developed by imec, different scenarios can be assessed quickly and the best option can be chosen in advance of a full design implementation.

Imec and Atrenta will be demonstrating the newest version of their advanced 3D planning and partitioning design flow in the Atrenta booth (1643) at DAC. The demonstration will include design partitioning across a 3D stack with routing congestion analysis, through silicon via (TSV) placement and backside redistribution layer routing support as well as display of thermal profiles on the 3D floor plan. For more information about Atrenta's demonstrations at DAC visit:
http://www.atrenta.com/DAC2011/sessions_short.html

About imec
Imec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China and Japan. Its staff of about 1,900 people includes more than 500 industrial residents and guest researchers. In 2010, imec's revenue (P&L) was 285 million euro. Further information on imec can be found at www.imec.be.
Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a "stichting van openbaar nut"), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands
(Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shangai) Co. Ltd.).

Contact:
Katrien Marent, Director of External Communications, T: +32 16 28 18 80
Mobile: +32 474 30 28 66, katrien.marent@imec.be

About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com

Atrenta, the Atrenta logo SpyGlass and GenSys are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

Contact:
Corporate: Charu Puri, Corporate Marketing
Tel: +1-408-467-4254
Email: cpuri@atrenta.com

PR Agency:
Lee PR
Ed Lee (ed@leepr.com)
Liz Massingill (liz@leepr.com)
Tel: +1-650-363-0142

STARC Adopts Atrenta's Advanced RTL Power and Deep Submicron Test Solutions

Wed, 18 May 2011 09:00:00 PST

San Jose, May 18, 2011 - Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced the adoption of Atrenta's latest 4.5 release of its SpyGlass® Power and DFT DSM solutions into version 5.0 of the STARCAD-CEL reference flow for RTL estimation, reduction and verification of low power designs. The STARCAD-CEL reference flow is provided by the Semiconductor Technology Academic Research Center (STARC).

"Atrenta's latest release of power and deep submicron test solutions for RTL power estimation, reduction and verification offer the right answer to address today's complex design challenges," said Nobuyuki Nishiguchi, vice president and general manager, R&D Department-2 at STARC. "The version 5.0 of the STARCAD-CEL Reference Flow includes Atrenta's SpyGlass Power and SpyGlass DFT DSM solutions, enabling our customers to find killer bugs and implement low power design strategies while saving multiple iterations of synthesis and tens of hours of power simulations at the gate level."

New un-instrumented RTL checks were added to the SpyGlass Power product to support verification of RTL designs with power strategies that enable downstream implementation tools to insert the correct level shifters and isolation logic. The new low-power DFT rules in the SpyGlass DFT DSM product were verified on the STARC design suite with CPF & UPF power intent data. These rules help to verify that correct "test control cells" are added to isolate the power management units (PMU) for scan-based testing. STARC engineers have also conducted an exhaustive evaluation of Atrenta's CPF & UPF power format support and power intent verification capability on over 100 test case designs with multiple voltage domains and power domains.

STARC evaluated the SpyGlass Power solution with both vectors and vector-less analysis for estimation of leakage power, data path and clock power. The RTL power estimation results of the latest SpyGlass 4.5 release have significantly improved over the previous releases. The power numbers at RTL were within 8.5% of gate level numbers with an improved runtime of 16% compared to the previous release. About a 40% power reduction was achieved on STARC designs with embedded memories by using the latest formal techniques included in the product.

"Atrenta is the only vendor to provide RTL power estimation, reduction and verification support with both CPF and UPF power format support for both design and test modes," said Kiran Vittal, product marketing director for clocks, power and test products at Atrenta. "STARC's thorough evaluation and adoption of SpyGlass Power into the STARCAD-CEL flow has once again validated the effectiveness of using early analysis solutions at RTL for both design and test on low power designs."

About SpyGlass Power
The SpyGlass Power solution provides early information about power consumption at RTL, and provides guidance where power can be reduced with respect to clock gating, memory and data path designs. The SpyGlass Power solution not only detects, but can also automatically fix key power management issues. SpyGlass Power also supports UPF and CPF power formats and verifies designs with voltage and power domain management structures so that voltage level shifters and isolation logic are correct. For more information, please visit
http://www.atrenta.com/solutions/spyglass-family/spyglass-power.htm

About SpyGlass DFT DSM
The SpyGlass DFT and SpyGlass DFT DSM solutions have the unique ability to predict ATPG (automatic test pattern generation) test coverage for both stuck-at and transition faults and pinpoint testability issues as the RTL description is developed, even before a gate-level netlist is generated. The SpyGlass DFT solution not only detects testability issues--it can also automatically correct them. For more information, please visit
http://www.atrenta.com/solutions/spyglass-family/spyglass-dft.htm

About Atrenta
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com

*******************************************************
Atrenta, the Atrenta logo SpyGlass and GenSys are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

For more information, contact:
Corporate:
Charu Puri, Corporate Marketing
Tel: +1-408- 467-4254
Email: cpuri@atrenta.com

PR Agency:
Lee PR
Ed Lee (ed@leepr.com)
Liz Massingill (liz@leepr.com)
Tel: +1-650-363-0142

Atrenta Ships the Industry's Most Comprehensive RTL Platform

Mon, 16 May 2011 00:00:00 PST

San Jose, Calif., May 16, 2011 - Atrenta Inc ., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, has announced the availability of the next-generation release of its popular SpyGlass® product family. SpyGlass 4.5 contains a number of innovations to further increase its impact across a broad range of advanced system on chip (SoC) designs and customer applications.

Atrenta has enhanced the SpyGlass family in multiple areas, including usability, debug, advanced linting, power estimation and reduction, CDC verification, constraints management, and testability. SpyGlass is widely installed throughout the semiconductor and systems industries. There are over 170 customers comprising thousands of users at companies such as Renesas Mobile and STMicroelectronics. SpyGlass has become the de facto standard for advanced SoC designs.

The core SpyGlass infrastructure now offers an industry-standard Tcl command line interface that enables RTL designers to create specialized scripts for repetitive tasks, perform interactive query and exploration, debug interactively and generate/customize reports.

Debugging has been strengthened significantly through additional abstractions in the incremental schematic - allowing the user to focus on the specific logic related to a violation, thus reducing debug effort. The concept of 'scenarios' has also been introduced to allow more intuitive analysis and management of configurable and/or multi-mode designs.

Based on advanced formal analysis techniques, the SpyGlass CDC product now leverages ground-breaking structural analysis technology to accelerate the process of identifying and resolving clock domain crossing (CDC) problems. This new technology applies class-leading techniques to pin-point only the real CDC issues in a design and minimize the effort required to debug and fix them. The new hierarchal CDC analysis capability using an abstracted model for already analyzed blocks enables significant runtime improvements and virtually unlimited capacity to handle very large SoC designs.

The performance of the SpyGlass Constraints product has been further enhanced in this release to offer run times which are at par with typical static timing analysis (STA) tools for netlist designs, while continuing to offer fast constraint analysis at the RTL stage of the design flow. Users have reported performance improvements of up to 5X. Users will also see performance improvements when identifying clock to clock false paths - both the synchronous and asynchronous varieties.

The SpyGlass DFT and SpyGlass DFT DSM products have been enhanced to provide new capabilities for SoC DFT debug including the verification of IEEE 1149.1 and IEEE 1500 setup sequences through high-level Tcl commands. SpyGlass DFT DSM also supports the CPF & UPF power intent formats to verify power management circuitry under test mode conditions. The SpyGlass MBIST product now supports a Tcl-based flow for RTL memory built-in self test insertion.

The SpyGlass Power product family has been enhanced to support new strategies for low power verification with industry-leading support for both the CPF & UPF power intent formats. The performance of power verification has been substantially improved, in many cases by over 30% based on customer design runs. The RTL power estimation and reduction capabilities have been enhanced to support newer techniques to reduce more power around registers and memories. These techniques have shown 40% reduction in power on representative customer designs. Both sequential equivalence checking and formal technology are employed in the SpyGlass Power family.

And finally, the popular SpyGlass DashBoard and DataSheet reports have a simplified report structure for easy portability, as well as a new look and feel that improves readability. These reports have found significant application in management dashboards for design tracking, audits, and development of rigorous handoff documentation to improve the quality of delivered IP.

SpyGlass 4.5 is now in production and available for download.

About Atrenta

Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com
*******************************************************
Atrenta, the Atrenta logo, SpyGlass and GenSys are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

For more info, please contact:
Atrenta Corporate:
Charu Puri, Corporate Marketing
Atrenta Inc.
Email: cpuri@atrenta.com
Tel: +1-408-467-4254

Atrenta PR Agency:
Ed Lee
Lee PR
Email: ed@leepr.com
Tel: +1-650-363-0142