The annual Design and Verification Conference – DVCon is being held this week, at the Doubletree Hotel in San Jose, CA. In case you had any trouble finding the agenda of the technical programs on the DVCon website, I have copied the links and schedule here:

Wednesday at DVCon:
February 25, 2009
7:00 AM
Breakfast: Prototyping: Where Hardware & Software First Meet(Pine/Cedar Ballroom)

8:15- 8:45
Opening Session (Oak Ballroom)

9:00-10:30
Session 1 (Fir Ballroom): Verification Methodology and Testbenches – I
Session 2 (Oak Ballroom) :Formal Verification Applications

11:00-12:30
Session 3 (Fir Ballroom) :Increasing Functional Coverage
Session 4(Oak Ballroom):Emulation/Acceleration

Lunch Presentation: Case Studies of OVM in Multi-language Verification Environment (Pine/Cedar Ballroom)

2:00-2:45
Keynote (Oak/Fir Ballroom):”The Techonomics of Verification”
Aart de Geus – CEO and Chairman of the Board – Synopsys, Inc.

3:15-5:00
Panel: EDA: Dead or Alive? (Oak/Fir Ballroom)

5:00-6:30pm
Cocktail Reception

Thursday at DVCon:

8:30-10:00
Session 5 (Donner Ballroom): Verification Methodology and Testbenches – II
Session 6 (Cascade Ballroom): Low Power Verification
Session 7 (Siskiyou Ballroom): Verification Data Management

10:30-12:00

Session 8 (Donner Ballroom): Verification Methodology and Testbenches -III
Session 9 (Cascade Ballroom): Mixed-signal Design and Verification
Session 10 (Siskiyou Ballroom): Case Studies – I

Lunch Presentation (Pine/Cedar Ballroom): Risky Business: How Do I Manage Risk in My Next Design Project?

1:30-3:00
Session 11 (Donner Ballroom): Low Power Management
Session 12 (Cascade Ballroom): Programming with SystemVerilog
Session 13 (Siskiyou Ballroom): Case Studies – II

3:30-5:00 (Donner/Siskiyou Ballroom)
Panel: Mixing Formal Analysis with Simulation: Why, When, Where, and How?

5:30-6:00 (Donner/Siskiyou Ballroom): Closing Session 2009 Best Paper Award Presentation

I will be attending Wednesday afternoon, and am particularly looking forward to the panel discussion: “EDA: Dead or Alive?” to be moderated by Peggy Aycinena.

Personally, I’d say EDA is not dead, but if you look at the industry overall it is pretty comatose. That could probably be said of the economy in general right now, but much of the problem in EDA is self-inflicted. As a student of economics and business management, I am actually looking forward to seeing the inefficiencies shaken out. A major re-structuring of the EDA industry is called for, so that it can better serve the needs of its customers. There is no room any more for all the redundancy, waste and sloppy management that has gone on for too many years. It should be interesting!

On Thursday, I will be attending the session on Mixed-signal Design and Verification:

Session Chair: Thomas J. Sheffler – Consultant

9.1 Validating WiMAX OFDMA using SystemVerilog and VMM
Albert Chiang, Wei-Hua Han – Synopsys, Inc.
Bhanu Kapoor – Mimasic

9.2 A SystemVerilog Approach for Analog/Mixed-signal Verification
Shyam Rapaka, Tapan Halder – Synopsys, Inc.
Vikas Chandra – ARM

9.3 Get to ASICs Faster – a Novel Mixed-signal Design Methodology
Greg Tumbush – Tumbush Enterprises, LLC
Gareth Weale, Dustin Griesdorf, William Gonnason, Marc Matthey, Andreas Drollinger, Alaa El-Agha – ON Semiconductor
Holger Meiners – Consultant

I hope to see many of you there.

-Mike